Equivalence Checking of Combinational Circuit Using Chaotic Pattern Simulation and Binary Decision Diagrams

With the increase of complexity of circuits, guaranteeing the correctness of design becomes extremely important. A new equivalence checking method is presented in this paper for the verifications of combinational circuits; the method uses the chaotic pattern simulation to find a lot of equivalent nodes, which results in that the scale of the composite circuit is reduced. The equivalence checking of two combinational circuits is carried out by constructing a BDD which is corresponding to a circuit being made up of the composite circuit and interface circuit. If the BDD is a constant 0, then the two combinational circuits are functional equivalence, the two rest circuits are not equivalent. The experimental results for a lot of circuits show that the more accurate equivalent nodes can be obtained by using chaotic pattern simulation in this paper than the random pattern simulation, and the equivalence checking method presented in this paper is able to verify the combinational circuits in shorter time.